1. Filed of the Invention
The present invention relates in general to semiconductor memory device fabrication processes. In particular, the present invention relates to the process for fabrication of high reliability flash memory devices. More particularly, the present invention relates to a process for fabrication of split-gate flash memory devices featuring self-alignment for improved endurance and reliability.
2. Technical Background
Conventional semiconductor fabrication processes for manufacturing split-gate flash memory devices employ photolithography techniques for defining channel dimensions of the transistors in memory cells of flash memory arrays. Since it is difficult to achieve an acceptable level of precision in photomasking alignments in the process of photolithography, fabricated split-gate memory devices can exhibit problematic operational characteristics.
For example, refer to the configuration of one typical prior art split-gate flash memory device as shown in FIGS. 1, 2 and 3. FIG. 1 shows a schematic plan view of the device. FIG. 2 shows a cross section of the FIG. 1 device taken along selected section II--II. FIG. 3 depicts and equivalent circuit schematic. As seen in FIG. 2, the memory cell of the typical split-gate flash memory device usually combines a floating-gate transistor 20 and an enhanced isolation transistor 22 on a P-type substrate 1. The memory cell includes floating gate 12, control gate 14, drain region 15, source region 16, layer of tunnel oxide 11, and gate dielectric 13. As is seen in FIG. 2, channel length L of the entire split-gate memory cell is generally equal to channel length L.sub.1 of floating-gate transistor 20 and channel length L.sub.2 of isolation transistor 22.
The memory cell having a structural configuration combining a floating-gate transistor and an enhanced isolation transistor features an important advantage in its inherent characteristics. During the process of memory erasure, however, to ensure complete removal of the electrons previously injected into the floating gate, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e., more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the floating-gate transistor becomes a depletion transistor, which conducts even in the absence of applying a high voltage at control gate 12. This phenomena is known in the art as memory over-erasure. Isolation transistor 22 in such a split-gate memory cell will keep in the OFF state even if floating gate transistor 20 is subjected to over-erasure and brought into the ON state. This isolation characteristic provided by isolation transistor 22 is important for the correct operation of the memory cell.
However, as indicated above, due to difficulties in achieving an acceptable level of alignment precision during the photolithographic fabrication process of such a split-gate memory cell, it is not easy to confine the dimensions of L.sub.1 and L.sub.2, i.e., the channel lengths of floating gate and isolation transistors 20 and 22 respectively, to within specified tolerances even when total channel length L of the memory cell is set to a fixed value. A mis-aligned distribution of channel lengths among the floating gate and isolation transistors would cause the memory cell to function unreliably. For example, if channel length L.sub.2 for isolation transistor 22 is insufficient, the desired isolation effect would not be obtained.
FIG. 4 shows the cross-sectional view of a split-gate memory cell fabricated in accordance with the teaching of the U.S. Pat. No. 4,868,629, issued on Sep. 19, 1989 to B. Eitan, entitled "Self-Aligned Split Gate EPROM." The memory cell is fabricated on P-type substrate 3 and includes floating gate 32, drain region 34, source region 36, and layer of tunnel oxide 30. Photoresist layer 38 is employed for alignment in defining the channels of the floating-gate and isolation transistors in the memory cell. The photomasking alignment difficulty will therefore apply to such a fabrication methodology. Since achieving acceptable dimensions in the channel lengths of the floating-gate and isolation transistors by this process is difficult, correct operation of the fabricated memory devices might be not obtained.
FIG. 5 shows the cross-sectional view of a split-gate memory cell fabricated in accordance with the teaching of U.S. Pat. No. 4,949,140, issued on Aug. 14, 1990 to S. M. Tam, entitled "EPROM Cell With Integral Select Transistor." The memory cell is fabricated on P-type substrate 4 and includes floating gate 42, control gate 44, source region 45, drain region 46, P-type implanted region 47, layer of tunnel oxide 41, and gate dielectric 43. In accordance with the disclosure, sidewall spacers are employed for defining the channel length of the isolation transistor, while the entire channel length of the memory cell, as well as the channel length of the floating-gate transistor included therein, is defined by the photolithography procedure. Therefore, this memory device may also suffer the problem of unreliable operation due to insufficient precision in the channel lengths.
Moreover, since these prior art memory cells all implement a memory cell erasure and writing operation from either source or drain side, such single-sided erasure and writing operation reduces the life expectancy and reliability of the device. This reduction is due to the fact that the floating gate 20 of this split-gate memory cell configuration is only provided near drain region 15, which results in different mechanisms occurring for the programming and erasing operations of the device. The resulting reduction of allowable program/erase cycles renders the device suitable only for those applications requiring a relatively few number of program/erase cycles during the entire life span of the device.